1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memories and, in particular, to semiconductor memories which include multistate EPROM or EEPROM cells.
2. Background Art
Non-volatile semiconductor memories including EPROMs (Electrical Programmable Read Only Memories) and EEPROMs (Electrically Erasable Programmable Read Only Memories) and Flash memories are becoming more popular. These memories utilize memory cells having a floating gate which is electrically isolated from the remainder of the cell and which stores an electrical charge indicative of the state of the cell.
Referring to the drawings, FIG. 1A shows one exemplary embodiment of a conventional flash memory cell 10. The cell 10 is formed in a P- type substrate 12, with an N+ type diffusion being formed in the substrate 12 to form the cell drain region 14. Cell 10 could also be formed in a P- type well, with term semiconductor body referring both to a substrate and a well. A graded N+/N- diffusion 16 is further formed in the substrate to from the source region. That portion of the substrate 12 intermediate the source and drain region is referred to as the channel region 12a and is the location where the N type channel is formed when the cell is rendered conductive. As defined herein, the drain region 14 for the subject N channel cells 10, as distinguished from the source region 16, is that region which is at the most positive voltage during read operations.
A floating gate 18, preferably fabricated from doped polysilicon, is disposed over the channel region 12a. A control gate 20, also preferably made of doped polysilicon, is disposed over the floating gate 18. The floating gate 18 is separated from the channel region 12a by a thin gate oxide layer which is typically 100 .ANG. thick. The floating gate 18 and the control gate 20 are separated from each other by a relatively thick interpoly dielectric 24.
The threshold voltage (V.sub.TH) of the cell 10 is defined herein as being that voltage applied to the control gate 20, relative to the source region 16, which causes a current to flow from the drain to the source (I.sub.DS) of 1 microampere when the drain to source voltage is +1 volt. In the case of flash memory cells and other types of floating gate devices, the threshold voltage V.sub.TH of the cell can be adjusted by changing the charge on the floating gate 18 during the programming of the cell. The magnitude of the threshold voltage V.sub.TH determines the state of the cell, that is, whether the cell is programmed to a "1" or a "0' state.
FIG. 1A shows the configuration of the cell 10 during a programming sequence. Initially, the cell 10 is in a completely erased state with no charge being present on the floating gate. A relatively large positive voltage V.sub.pp, typically +10 to +12 volts, is applied to the control gate and the source region 14 is grounded (V.sub.SS). In addition, the drain region is connected to an intermediate voltage VDD of typically +6 to +9 volts. These conditions cause electrons to exit the source region and travel towards the drain region 14. The electrons will be injected from the channel region 12a and onto the floating gate 20 by virtue of the positive voltage on the control gate 20 by a mechanism commonly referred to as CHE (channel hot electron). As is well known, the presence of the negative electric charge on the floating gate alters the threshold voltage of the cell, with a programmed cell 10 typically being assigned the arbitrary logic state of "0". An unprogrammed cell 10, one that is in the erased state, is thus assigned the logic state of "1".
FIG. 1B depicts the conditions for reading the flash memory cell 10. The source region is grounded (V.sub.SS) and a positive voltage V.sub.CC is applied to the control gate 20. Voltage V.sub.CC, which is the primary memory supply voltage, is typically +5 volts. In addition, positive voltage V.sub.R is applied to the drain region. Voltage V.sub.R, which is derived from an active load divider (not depicted) connected to voltage V.sub.CC, is typically +1 volts.
Assuming that the cell 10 being read is in the original erased state, that is, the cell has not been programmed, the threshold voltage V.sub.TH will be relatively low. The magnitude of the voltage V.sub.CC applied to the control gate 20 will be sufficient to invert the channel region 12a so that an N type channel will be formed between the drain and source regions. The flow of drain/source current I.sub.DS will result in an increase in voltage dropped across the active load which will be detected by a sense amplifier (not depicted) connected between the drain region 14 and voltage V.sub.CC. The sensed change in voltage indicates that the cell being read is in a given logic state ("1").
In the event the cell 10 being read had been previously programmed, the presence of negative charge on the floating gate 18 will effectively increase the threshold voltage V.sub.TH of the device. In that event, the applied source-control gate voltage V.sub.CC will not be sufficient to invert the channel region 12a. The cell 10 will remain non-conductive and the voltage at the drain (V.sub.R) will remain unchanged. The sense amplifier, connected to the drain of the cell, will interpret cell 10 to be in a state ("0") opposite to that when the cell remains in an erased, low threshold voltage state ("0").
The cell 10 is erased under the conditions shown in FIG. 1C. The drain region 14 is left floating (F) and the source region 16 is connected to positive voltage V.sub.CC. In addition, a negative voltage V.sub.EE is applied to the control gate 20. The resultant electric field causes electrons to be removed from the floating gate 20 to the source region 16 by way of Fowler-Nordheim tunneling.
It is possible during an erase sequence to create what is sometimes referred to as an "over erase" condition wherein the number of electrons removed from the floating gate 18 is such that a net positive charge is formed on the floating gate. This net positive charge on the floating gate can be of sufficient magnitude such that the channel region 12a remains inverted (N type) even when the control gate 20 is at ground potential. Thus, the cell 10 is operating in a depletion mode as opposed to the normally-desired enhancement mode. This condition (depletion mode operation) is generally avoided because an overerased cell will be in a conductive state even when the cell has been deselected in a memory read operation. The resultant I.sub.DS current in the deselected cell will tend to mask the current (or lack of current) flow through the selected cell.
It is well known that the data storage density of memory cells, including flash memory cells, can be increased by increasing the number of memory states for each cell from two (one bit) to a larger number such as four (two bits), eight (three bits), and so forth. By way of example, U.S. Pat. No. 5,043,940 entitled "Flash EEPROM Memory Systems Having Multistate Storage Cells" discloses a technique wherein each cell is capable of storing a multiple number of bits using a split channel flash memory cell.
FIG. 2 shows a typical exemplary prior art split channel flash memory cell 26 of the type disclosed in the above-noted U.S. Pat. No. 5,043,940. The split channel cell, sometimes referred to as a split gate cell or a one and one-half transistor cell, is formed in a P- type substrate 12 and includes an N+ type drain region 14 and an N+ type source region 16 separated by a channel region split between regions segments 12a and 12b. A polysilicon floating gate 18 is disposed over channel region segment 12a, but not segment 12b. The floating gate 18 is separated from the channel segment 12a by a thin (typically 100 .ANG.) gate oxide 22.
Split channel cell 26 further includes a polysilicon control gate 20 having one segment 20a overlying the floating gate 18 and separated from the floating gate 18 by an interpoly dielectric 24. The control gate 20 includes another segment 20b separated from channel segment 12b by the gate oxide 22.
Operation of the split channel cell 26 is similar to that of the single transistor cell 10 of FIG. 1 in many respects. The cell 26 can be viewed as having two threshold voltage--one associated with channel segment 12a and one associates with channel segment 12b. The threshold voltage associated with segment 12b remains fixed and may be, by way of example, +1.5 volts. The threshold voltage associated with channel segment 12a will vary with the charge present on the floating gate 18 and may vary from +5 volts to +1 volt.
It is possible to overerase cell 26 in the same manner as the single transistor cell 10. In that event, channel segment 12a will become inverted (N type) and the threshold voltage associated with segment (V.sub.Ta) will become negative. However, channel segment 12b will not become inverted since the floating gate 18 does not overlie that portion of the channel. Thus, even if the control gate 20 is grounded, thereby permitting channel segment 12a to remain inverted, the threshold voltage associated with channel segment 12b (V.sub.Tb) will not be exceeded. Since channel segments 12a and 12b are connected in series, the cell 26 will remain non-conductive when the control gate 20 is grounded (when the cell is deselected), notwithstanding the fact that the cell was overerased.
The FIG. 2 cell 26 can, as disclosed in the above-noted U.S. Pat. No. 5,043,940, be implemented in a memory array having more than two states per cell. This is accomplished by programming/erasing the cell 26 so that there are four distinct threshold voltages V.sub.Ta associated with the channel segment 12a thereby providing four distinct states. It is desirable to maximize the voltage separation between the four states so as to provide greater operation reliability due to increased sense margin. This can be accomplished by erasing/programming the cells to have both negative and positive threshold voltages V.sub.Ta.
A negative threshold voltage V.sub.Ta means that the net charge on the floating gate 18 is positive, a condition similar to the above-described overerase condition previously described in connection with FIG. 1. Thus, the threshold voltage V.sub.Ta of the cell 26 may be, by way of example, +4.5 volts (State "0"), +2.0 volts (State "1"), -0.5 volts (State "2") and -3.0 volts (State "3"). When cell 26 is read, the typical conditions are depicted in FIG. 2. The source region 16 is grounded (V.sub.SS) and the drain region is connected to voltage V.sub.R which is derived from a higher voltage through an active voltage divider network. A voltage V.sub.CC of typically +5 volts is applied to the control gate 20. The voltage V.sub.CC is sufficient to invert channel segment 12b which has a fixed threshold voltage of typically +1 volt. The voltage V.sub.CC is also sufficient to invert channel segment 12a so that the cell 26 is rendered conductive. The magnitude of the resultant drain/source current I.sub.DS is a function of the variable threshold voltage V.sub.Ta. Using a sense amplifier arrangement to differentiate between the four possible values of I.sub.DS, it is possible to determine the programmed state of the cell 26.
As is well known, the cells 26 are typically arranged in an array having a plurality of rows and columns. All of the cells in a particular column typically have their sources and drains connected to respective bit lines and all of the cells in a particular row are connected to a common word line. As is well known, a particular cell in the array is selected for reading by applying the appropriate voltages shown in FIG. 2 to the appropriate bit and word lines. Other cells in the same row are deselected during the read sequence by grounding the bit line connected to the drains 14 of the cells, as opposed to applying voltage VR to the selected cell. Other cells in the same column as the selected cell are deselected by grounding the word line connected to the control gate 20. A grounded control gate 20 for the FIG. 2 split channel cell 26 will insure that current does not flow notwithstanding the fact that the cell may be programmed to have a negative threshold voltage V.sub.Ta. This is because the threshold voltage V.sub.Tb associated with channel segment 12b will be at a fixed positive voltage of typically +1 volts. Thus, the deselected ones of cells 26 will not be turned on, thereby permitting the selected cell 26 to be properly read.
The previously described multistate cell 26 thus provides increased data storage density since each cell is capable of storing more than one bit of data. However, the split channel (one and one-half transistor) configuration of the cell 26 as shown in FIG. 2 requires more area to implement than does simpler cell configurations such as single transistor cell 10 shown in FIG. 1. Furthermore, the overall threshold voltage V.sub.TH of the split channel cell 26 is a function of the both the fixed threshold voltage associated with channel segment 12b and the variable threshold voltage associated with channel segment 12a. The fixed threshold voltage component tends to diminish the influence of the variable component such that the voltage margin between states is smaller than it would otherwise be in the case of a single transistor cell 10 as shown in FIGS. 1A-1C. However, the single transistor cell 10 does not have a split channel to overcome the above-described problem which arises when the cell 10 has been programmed to a state where the threshold voltage V.sub.TH is negative, that is, when the cell has been programmed into the depletion mode.
The present invention is directed to a memory system having single transistor cells which are capable of multistate memory operation, that is, storing a multiplicity (three or more) of states so as to enhance memory density. It is further possible to program the cells over a wide range of threshold voltages V.sub.TH, including negative voltages, so as to increase the reliability of memory read operations. The advantage of increased voltage margin between states is provided since the single transistor cell does not have the fixed threshold voltage component associated with split channel cells. Further, smaller geometry single transistor cells provide enhanced memory density in comparison to split channel cells. These and other advantages of the subject invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.